1. Field of the Invention
The present invention relates to a controller for controlling the frame refresh rate of an active matrix display. The present invention also relates to a display controller including such a frame rate controller and to an active matrix display including such a controller. Such displays may be used in portable equipment where data may be supplied to the display in a variety of formats and where it is desired to minimise display power consumption.
2. Description of the Related Art
FIG. 1 of the accompanying drawings shows a typical active matrix liquid crystal display of known type. The display comprises an active matrix 1 of N rows and M columns of picture elements (pixels). Each pixel comprises a pixel electrode 2 facing a counter electrode (not shown) with a layer of liquid crystal material (not shown) therebetween. The pixel electrode is connected to the drain of a pixel thin film transistor (TFT) 3, whose source is connected to a data line 4, which is common to all of the pixels of a column, and whose gate is connected to scan line 5, which is common to all of the pixels of a row.
The data lines 4 are connected to a data line driver 6, which receives timing, control and data signals from a data controller (not shown) and which supplies analogue voltages for charging the data lines 4. The scan lines 5 are connected to a scan line driver 7 which is controlled by the timing signals and which supplies scan line pulses to the scan lines 5 one at a time in a cyclically repeating sequence.
Image data are transmitted to the data driver on a frame by frame basis. Within each frame, image data are transmitted line by line with each line of data corresponding to the required display states of a horizontal row of pixels of the display. The lines of data are loaded one at a time into the data line driver 6 which charges the data lines 4 to the required voltages. The scan line driver 7 then supplies a scan pulse to the row of pixels to be updated. The pixel transistors 3 of the row receive the scan pulse at their gates and are switched to a conductive state so that the voltages on the data lines 4 charge the pixel electrodes 2 of the line being refreshed. This is repeated row by row until the whole display has been refreshed by a fresh frame of data. This is then repeated for each frame of data.
FIG. 2 of the accompanying drawings illustrates a typical liquid crystal display controller 10 in the form of an integrated circuit which is generally physically separate from the display. The controller 10 comprises a timing generator 11 which receives clock signals (CKS), horizontal synchronisation signals (HS) and vertical synchronisation signals (VS). The timing generator 11 passes these timing signals to the display and generates timing signals for controlling the operation of the display controller 10.
The controller 10 is capable of receiving video data in either luminance and chrominance format (Y, Cr, Cb) or in RGB (red, green, blue) format. A matrix 12 converts the chrominance format data into RGB format data. An on-screen display mixer 13 receives the RGB data either from the matrix 12 or directly from an RGB input and mixes this as desired with on-screen data from an external static random access memory (SRAM) 14 so that any on-screen display data overwrite the video data. The RGB outputs of the mixer 13 are connected to a gamma correction circuit 15, which compensates for the non-linear response of the pixels to voltage and which allows picture adjustments to be made, for example to the colour, brightness and tint of the displayed image.
The RGB outputs of the gamma correction circuit 15 are supplied in parallel digital format to a digital output 16 for use with displays which require digital input video data. For displays which require analogue input data, the outputs of the gamma correction circuit 15 are supplied to a digital/analogue converter (DAC) 17, which converts the red, green and blue image data to corresponding analogue voltage levels. These voltage levels are amplified by an amplifier 18 and supplied to an analogue output 19.
In typical liquid crystal controller integrated circuits, the frequency of the data can be adjusted to the particular requirements of the display. For example, the controller 10 may output data in either SVGA format or XGVA format, which have different data transmission rates for a given frame rate. The frame rate itself is typically fixed to a frequency which is characteristic of the refresh rate required by the liquid crystal material of the display.
In displays which are for use in portable or battery-powered equipment, it is desirable to reduce the power consumption as much as possible so as to prolong battery life and reduce the frequency of replacing batteries. U.S. Pat. No. 5,926,173 discloses a power saving technique for such a display in which, when new image data are sensed as being supplied to the liquid crystal display (LCD), the power supply to the LCD is stopped. U.S. Pat. No. 5,757,365 discloses another power saving technique for display drivers, in which the absence of image data is also sensed. When this is the case, the drivers, which contain a frame memory, operate in a lower power self-refreshing mode.
U.S. Pat. No. 5,712,652 discloses a portable computer having an LCD. This patent specification discloses reducing the refresh rate of a video graphics controller so as to reduce power but does not describe any technique for achieving this.
U.S. Pat. No. 6,054,980 discloses an arrangement for providing frame rate conversion between a computer supplying display data at one frame rate and a display device which cannot operate at such a high frame rate, but in which the supply and display frame rates are not greatly different from each other. This is achieved by the use of a frame buffer in which image data are written at the supply rate and are read at the display rate so that each (N+1)th frame of image data is effectively dumped, where N is an integer greater than zero.
U.S. Pat. No. 5,991,883 discloses a technique for managing power consumption in laptop computers and the like. The display refresh rate is adapted according to the type of images which are to be displayed. A reduced refresh rate is achieved by reducing the processing speed of image data, for example by reducing the pixel clock rate of a video graphics controller.
U.S. Pat. No. 5,446,840 discloses reducing the rate at which video data are supplied so as to take some of the processing burden off the CPU of a computer system running graphical user interfaces. New video data are written to a relatively fast RAM and then refreshing or updating a display device takes place at a relatively slow rate which is just fast enough to avoid undesirable perceptible visual artefacts.